1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and particularly to a semiconductor integrated circuit including I/O cells and pads.
2. Description of the Related Art
In recent years, semiconductor integrated circuits have been used in a variety of fields and demand for large-scale integration circuits (LSIs) has been growing. Along with such growth, further integration and reduction in size of LSIs are becoming increasingly important for reasons such as reduction of manufacturing costs.
In view of this, internal circuitry of LSIs has been further integrated and reduced in area owing to techniques for miniaturization of transistors. On the other hand, integration of a system on an LSI increases the size of an I/O area in which an external interface circuit of the LSI is placed. In addition, the size of the I/O area is further increased as a trade off for improvement in characteristics of the interface circuit required for higher functionality and higher speed. In this manner, a phenomenon exists that the I/O area increases in size while the internal circuit is further integrated and reduced in area.
FIG. 9 is a plan view showing a configuration of an I/O unit (input-output circuit) included in a conventional semiconductor integrated circuit.
The I/O unit 700 shown in FIG. 9 includes I/O cells 701 and 711, bonding pads (PADs) 702 and 712, via contact holes (VIAs) 704 and 714, package wires 706 and 716, and bonding fingers 707 and 717.
In addition, the conventional I/O unit 700 has an I/O area 750 between an LSI external boundary 752 and an LSI internal circuit boundary 751.
The I/O cells 701 and 711 are placed in the I/O area 750. The I/O cell 701 is an I/O cell for a first signal, and the I/O cell 711 is an I/O cell for a second signal.
The I/O cell 701 includes an internal wiring 705. The I/O cell 711 includes an internal wiring 715.
The PAD 702 is positioned closer to the internal circuit (on the side closer to the LSI internal circuit boundary 751) than the PAD 712 is.
The PAD 702 is connected to the package wire 706 at a connection point 703. The PAD 712 is connected to the package wire 716 at a connection point 713.
The VIA 704 connects the internal wiring 705 and the PAD 702. The VIA 714 connects the internal wiring 715 and the PAD 712.
In the I/O unit 700, although the distance between the LSI internal circuit boundary 751 and the VIA 704 is short, wire resistance and wire inductance for the first signal is high because the package wire 706 is long. On the other hand, although the package wire 716 is short, resistance of the I/O cell internal wiring 715 for the second signal is high because the distance between the LSI internal circuit boundary 751 and the VIA 714 is long.
A technique to solve such a problem has been presented for reducing the resistance of the internal wiring 705 and 715 and the resistance of the package wires 706 and 716.
FIG. 10 is a plan view showing a configuration of an I/O unit 800 with improved characteristics, included in a conventional semiconductor integrated circuit. Components also shown in FIG. 9 are denoted with the same reference numerals, and thus a description thereof is omitted.
In addition to the components of the I/O unit 700, the I/O unit 800 shown in FIG. 10 includes I/O cells 801 and 811, PADs 802 and 812, VIAs 804 and 814, package wires 806 and 816, bonding fingers 807 and 817, and package internal wirings 808 and 818.
The I/O cell 801 is an additional I/O cell for the first signal and the I/O cell 811 is an additional I/O cell for the second signal.
The I/O cell 801 includes an internal wiring 805. The I/O cell 811 includes an internal wiring 815.
The PADs 702 and 812 are positioned closer to the internal circuit than the PADs 712 and 802 are, respectively.
The PAD 802 is connected to the package wire 806 at a connection point 803. The PAD 812 is connected to the package wire 816 at a connection point 813.
The VIA 804 connects the internal wiring 805 and the PAD 802. The VIA 814 connects the internal wiring 815 and the PAD 812.
The package internal wiring 808 connects the bonding finger 707 and the bonding finger 807. The package internal wiring 818 connects the bonding finger 717 and the bonding finger 817.
In the above configuration, the I/O unit 800 has two sets of the I/O cell, the PAD, and the package wire for each of the signals. The two sets are connected in parallel for the corresponding signal. As a result, the resistance of the internal wirings and the package wires is reduced, and therefore characteristics of the I/O unit 800 are improved compared with those of the I/O unit 700.
However, the size of the I/O area 750 of the I/O unit 800 is approximately twice as large as that of the I/O unit 700.
In addition to the above technique, a configuration has been presented as a method of reducing the area of the I/O area 750 in which a plurality of pads is provided inside the I/O cell (for example, see Japanese Unexamined Patent Application Publication Number 11-330371 (Patent Reference 1)).
As described above, the I/O unit 800 according to a conventional technique further includes a set of an I/O cell and a PAD provided to each of the existing I/O cells so that the resistance and inductance of a connection unit (including a package wire, a package internal wiring, a package ball, a bump, or a leadframe), which provides an external connection to the existing PAD, are reduced. Accordingly, the size of the I/O area of the I/O unit 800 is twice as large as the size of the I/O area 750. That is, there is a problem with the conventional I/O unit 800 that characteristics improvement necessitates increase in the chip area.
In addition, the I/O structure presented in Patent Reference 1 has a problem that the plurality of the pads provided in the I/O cell unnecessarily increases the I/O area 750 in size.
The present invention has an object of providing a semiconductor integrated circuit in which a part providing an external connection to an internal circuit has a reduced resistance and increase in the size of an I/O area is reduced.